1. Field of the Invention
The present invention relates to a solid-state image taking device adopting an all-pixel read method for reading out pieces of electric charge at the same time from opto-electrical conversion elements each employed in one of all unit pixels forming a pixel array and relates to an electronic apparatus in which the device is embedded.
2. Description of the Related Art
One of typical examples of the solid-state image taking device is a CMOS image sensor for reading out opto-electric charge, which has been accumulated in a PN junction capacitor of a photodiode serving as the opto-electric conversion element (also referred to hereafter as an opto-electric conversion section) of every unit pixel employed in the CMOS image sensor, through a MOS transistor of the pixel. The CMOS image sensor carries out an operation to read out pieces of opto-electric charge, which each have been accumulated in a photodiode, for every predetermined unit such as a pixel or a row of pixels. Opto-electric charge is signal electric charge obtained as a result of an opto-electric conversion process carried out by the photodiode. Thus, an exposure period during which opto-electric charge is accumulated cannot be made uniform for all pixels employed in the CMOS image sensor. As a result, a distortion is generated at an image taking time typically for a case in which an image taking object moves.
Typical Configuration of a Unit Pixel of the CMOS Image Sensor
FIG. 1 is a diagram showing the configuration of a unit pixel 100 employed in a CMOS image sensor according to an existing technology disclosed in Japanese Patent Laid-open No. 2009-268083 (hereinafter referred to as Patent Document 1).
As shown in FIG. 1, the unit pixel 100 employs a PD (photodiode) 101, a transfer gate transistor 102 denoted by reference symbol TRG and an N-type area 103 composing an FD (floating diffusion) capacitor denoted by reference symbol FD in the figure. In addition, the unit pixel 100 also has a reset transistor 104, an amplification transistor 105 and a select transistor 106.
In the unit pixel 100, the photodiode 101 is an embedded photodiode created by typically forming a P-type layer 113 on the surface of a P-type well layer 112 constructed on a semiconductor substrate 111 and embedding an N-type embedded layer 114 beneath the P-type layer 113. The transfer gate transistor 102 transfers electric charge accumulated in the PN junction of the photodiode 101 to the N-type area 103 composing the floating diffusion capacitor FD.
In the CMOS image sensor, the unit pixels 100 each having the configuration described above are laid out to form a unit-pixel matrix serving as an image taking section.
In the image taking section, the amount of signal electric charge transferred by the transfer gate transistor 102 from the photodiode 101 to the N-type area 103 is determined by a timing to apply a transfer pulse TRG to the gate electrode of the transfer gate transistor 102. A method of applying the transfer pulse TRG to the gate electrode of the transfer gate transistor 102 employed in every unit pixel at the same time is known as the all-pixel read method mentioned before.
Mechanical-Shutter Method
By the way, a typical example of a method for implementing an exposure operation of an image taking operation during almost simultaneous exposure periods for all pixels is a widely utilized mechanical-shutter method making use of a mechanical shutter serving as mechanical light shielding means.
This mechanical light shielding means carries out the exposure operation by starting the exposure period almost at the same time for all pixels and terminating the exposure period also almost at the same time for all the pixels.
In accordance with the mechanical-shutter method, the exposure periods are mechanically controlled in order to make the exposure periods all but uniform for all unit pixels. The exposure period is a period during which light incident to the photodiode 101 is converted into opto-electric charge serving as signal electric charge. Then, when the mechanical shutter is closed, the unit pixel enters a state in which actually no opto-electric charge is generated in the photodiode 101. After the mechanical shutter has been closed, the signal electric charge is sequentially read out from the photodiode 101. Since the mechanical-shutter method requires that the mechanical light shielding means be used, however, it is difficult to reduce the size of the CMOS image sensor. In addition, since there is a limit on the mechanical driving speed of the mechanical light shielding means, the simultaneity of mechanical-shutter method is inferior to that of an electrical method.
All-Pixel Simultaneous Read Operation Using an Electronic Shutter (Global Exposure)
In order to prevent a distortion from being generated at an image taking time as described above, an image taking operation is carried out by making use of an electronic shutter to execute electrical control for setting an all-pixel simultaneous exposure period. The operation carried out for setting this all-pixel simultaneous exposure period is referred to as the so-called global exposure operation. By referring to FIG. 1, the following description explains steps (1) to (6) of a procedure of the global exposure operation disclosed in documents such as Patent Document 1.
Step (1)
Light incident to the photodiode 101 is subjected to an opto-electric conversion process of converting the light into signal electric charge in the semiconductor substrate 111. In the case of the configuration shown in FIG. 1 for example, electrons serving as the signal electric charge are accumulated in the N-type embedded layer 114 whereas holes are discarded from a P-type area not shown in the figure to the outside. Some holes are caught by the P-type layer 113 so that the signal electric charge is not trapped at a substrate surface level introduced by a defect and the caught holes serve as fixed electric charge having an effect on the electrons accumulated in the N-type embedded layer 114. As a result, the quantity of the saturated electric charge accumulated in the N-type embedded layer 114 is stabilized.
Step (2)
When a transfer pulse TRG is applied to the gate electrode of the transfer gate transistor 102, an electric-charge exhausting operation is carried out at the same time on all unit pixels in order to discard electric charge accumulated in the photodiode 101 employed in every unit pixel, that is, in order to make the photodiode 101 empty.
Then, in an exposure operation, on the other hand, signal electric charge (that is, opto-electric charge) obtained as a result of an opto-electric conversion process is accumulated in the PN junction capacitor of the photodiode 101.
Step (3)
At the end of the exposure period during which the exposure operation described above is carried out, the transfer pulse TRG is again applied to the gate electrode of the transfer gate transistor 102 in order to turn on the transfer gate transistor 102 of every unit pixel 100 for all unit pixels 100 at the same time. With the transfer gate transistor 102 turned on, all the electric charge accumulated in the photodiode 101 employed in every unit pixel 100 is transferred to the N-type area 103 serving as the floating diffusion capacitor FD of the unit pixel 100 for all unit pixels 100 at the same time. On the falling edge of the transfer pulse TRG applied to the transfer gate transistor 102 for the second time, the transfer gate transistor 102 is turned off, entering a closed state. Thereafter, the opto-electric charge accumulated in the photodiode 101 of every unit pixel 100 during the same exposure period for all the unit pixels 100 is held in the floating diffusion capacitor FD employed in the same unit pixel 100.
Step (4)
The amplification transistor 105 amplifies a signal level representing the amount of the signal electric charge held in the N-type area 103. When a select pulse SEL is applied to the gate electrode of the select transistor 106, the amplified signal level is asserted on a vertical signal line 200 in the so-called D phase read operation. The D phase read operation to read out the amplified signal can be carried out for every unit pixel 100. In this procedure, however, the operation to read out the amplified signal is carried out for every row of unit pixels 100 on a one-row-after-another basis.
Step (5)
Then, when a reset pulse RST is applied to the gate electrode of the reset transistor 104, the amount of electric charge held in the N-type area 103 is reset.
Step (6)
Thereafter, the select pulse SEL is again applied to the gate electrode of the select transistor 106 in order to assert a reset level on the vertical signal line 200 in the so-called P phase read operation.
After the signal level and the reset level have been asserted on the vertical signal line 200, in signal processing carried out at a later stage, the reset level is used to eliminate noises from the signal level.
Structure of Unit Pixel Having a Memory
Patent Document 1 and Japanese Patent Laid-open No. Hei 11-177076 (hereinafter referred to as Patent Document 4), Japanese Patent Laid-open No. 2006-311515 (hereinafter referred to as Patent Document 5), and Japanese Patent Laid-open No. 2008-004692 (hereinafter referred to as Patent Document 6) disclose the structure of a unit pixel further having a memory section added to the configuration shown in FIG. 1. In some cases, the memory section is also referred to as an electric-charge storage section.
FIG. 2 is a diagram showing the configuration of a unit pixel 300 including a memory section 107 described in Patent Document 1.
In addition to the N-type area 103 created in the P-type well layer 112 on a silicon substrate serving as the semiconductor substrate 111 to serve as the floating diffusion capacitor FD, the unit pixel 300 shown in FIG. 2 also employs the memory section 107 denoted by reference symbol MEM in the figure. In the same way as the N-type area 103, the memory section 107 is created from an N-type semiconductor area. The memory section 107 is used for temporarily stored opto-electric charge accumulated in the photodiode 101 and transferred from the photodiode 101. A transfer gate transistor 108 denoted by reference symbol TRX is provided between the photodiode 101 and the memory section 107 to function as means for controlling a transfer channel between the photodiode 101 and the memory section 107. To put it concretely, opto-electric charge accumulated in the photodiode 101 is transferred to the memory section 107 by way of the transfer gate transistor 108.